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? 2007 microchip technology inc. ds22035b-page 1 tc1270a/70an/71a features: ? precision voltage monitor - 2.63v, 2.93v, 3.08v, 4.38v and 4.63v trip points (typical) ? manual reset input ? reset time-out delay: - standard: 280 ms (typical) - optional: 2.19 ms, and 35 ms (typical) ? power consumption 15 a max ? no glitches on outputs during power-up ? active low output options: - push-pull output and open-drain output ? active high output option: - push-pull output ? replacement for (specification compatible with): - tc1270, tc1271 - tcm811, tcm812 ? fully static design ? low voltage operation (1.0v) ? esd protection: - 4 kv human body model (hbm) - 400v machine model (mm) ? extended (e) temperature range: -40c to +125c ? package options: - 4-lead sot-143 - 5-lead sot-23 - pb-free device package types functional block diagram device features 1 2 4 3 tc1271a sot-143 v ss v dd rst mr 1 2 4 3 tc1270a sot-143 v ss v dd rst mr 1 2 3 5 4 tc1271a sot-23-5 1 2 3 5 4 sot-23-5 nc nc v dd mr rst v ss v ss v dd mr rst tc1270a tc1270an 18.5 k v dd mr rst rst glitch filter voltage detector pp pp output driver circuitry (tc1271a) (tc1270a) reset generator & delay timer (2.19 ms, 35 ms, 280 ms) od rst (tc1270an) device output reset delay (ms) (typ) (3) reset trip point (v) (3) voltage range (v) temperature range packages comment type active level tc1270a push-pull low 2.19, 35, 280 (1) 4.63, 4.38, 3.08, 2.93, 2.63 (4) 1.0v to 5.5v -40c to +125c sot-143 (2) , sot-23-5 replaces tc1270 and tcm811 tc1270an open-drain low sot-23-5 new option tc1271a push-pull high sot-143 (2) , sot-23-5 replaces tc1271 and tcm812 note 1: the 280 ms reset delay time-out is compatible with the tc1270, tc1271, tcm811, and tcm812 devices. 2: the sot-143 package is compatible with the tc1270, tc1271, tcm811, and tcm812 devices. 3: custom reset trip points and reset delays available, contact factory. 4: the tc1270/1 and tcm811/12 1.75v trip point option is not supported. voltage supervisor with manual reset input
tc1270a/70an/71a ds22035b-page 2 ? 2007 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? supply voltage (v dd to v ss ) ...............................+7.0v input current, v dd ..............................................10 ma output current, reset , reset ........... .............10 ma voltage on all inputs and outputs w.r.t. v ss ............................ -0.6v to (v dd + 1.0v) storage temperature range ..............-65c to +150c operating temperature range...........-40c to +125c maximum junction temperature, t s ................... 150c esd protection on all pins human body model ....................................... 4kv machine model .............................................. 400v ? notice: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stre ss ratings only and functional operation of the device at those or any other conditions above those indicated in the operational listing of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics electrical characteristics: unless otherwise noted, v dd = 5v for l/m versions, v dd = 3.3v for t/s versions, v dd = 3v for r version, t a = -40c to +125c. typical values are at t a = +25c. parameter sym min typ (1) max units test conditions operating voltage range v dd 1.0 ? 5.5 v supply current i dd ?715av dd > v trip , for l/m/r/s/t, v dd = 5.5v ?4.7510 av dd > v trip , for r/s/t, v dd = 3.6v ?1015 av dd < v trip , for l/m/r/s/t reset trip point threshold (3) v trip 4.54 4.63 4.72 v tc127xal: t a = +25c 4.50 ? 4.75 v t a = ?40c to +125c 4.30 4.38 4.46 v tc127xam: t a = +25c 4.25 ? 4.50 v t a = ?40c to +125c 3.03 3.08 3.14 v tc127xat: t a = +25c 3.00 ? 3.15 v t a = ?40c to +125c 2.88 2.93 2.98 v tc127xas: t a = +25c 2.85 ? 3.00 v t a = ?40c to +125c 2.72 2.77 2.82 v tc127xa: (5) t a = +25c 2.70 ? 2.85 v t a = ?40c to +125c 2.58 2.63 2.68 v tc127xar: t a = +25c 2.55 ? 2.70 v t a = ?40c to +125c note 1: data in the typical (?typ?) column is at 5v, +25 c, unless otherwise stated. 2: r st output for tc1270a, and tc1270an, rst output for tc1271a. 3: tc127xa refers to either the tc1270a, tc1270an or tc1271a device. 4: hysteresis is within the v trip(min) to v trip(max) window. 5: custom ordered voltage trip point. minimum order volume requirement. 6: this specification allows this device to be used in pic? microcontroller applications that require the in-circuit serial programming? (icsp?) feature (s ee device-specific programming specifications for voltage requirements). the total time that the rst pin can be above the maximum device operational voltage (5.5v) is 100s. current into the rst pin sh ould be limited to 2 ma. it is recommended that the device operational temperature be maintained between 0c to +70c (+25c preferred). for additional information, refer to figure 2-41 .
? 2007 microchip technology inc. ds22035b-page 3 tc1270a/70an/71a reset threshold tempco ? 30 ? ppm/c reset trip point hysteresis (4) v hys ? 0.3 ? % percentage of v trip voltage mr input high threshold v ih 2.3 ? ? v v dd > v trip(max) , l/m only 0.7 v dd ?? vv dd > v trip(max) , r/s/t only mr input low threshold v il ??0.8 vv dd > v trip(max) , l/m only ? ? 0.25 v dd vv dd > v trip(max) , r/s/t only mr pull-up resistance 10 18.5 40 k open-drain high voltage on output v odh ? ? 13.5 v open-drain output pin only. v dd = 3.0v, time voltage > 5.5 applied 100s. current into pin limited to 2 ma +25c operation recommended (note 6) reset output voltage low (2) tc1270a/ tc1270an v ol ? ? 0.3 v r/s/t only, i sink = 1.2 ma, v dd = v trip(min) tc1271a ? ? 0.3 v r/s/t only, i sink = 1.2 ma, v dd = v trip(max) tc1270a/ tc1270an ? ? 0.4 v l/m only, i sink = 3.2 ma, v dd = v trip(min) tc1271a ? ? 0.3 v l/m only, i sink = 3.2 ma, v dd = v trip(max) tc1270a/ tc1270an ? ? 0.3 v l/m only, i sink = 50 a, v dd > 1.0v reset output voltage high (2) tc1270a v oh 0.8 v dd ? ? v r/s/t only, i source = 500 a, v dd = v trip(max) tc1270a v dd - 1.5 ? ? v l/m only, i source = 800 a, v dd = v trip(max) tc1271a 0.8 v dd ?? vi source = 500 a, v dd v trip(min) input leakage current i il ??1av pin = v dd open-drain rst output leakage i olod ? ? 1 a open-drain configuration only. capacitive loading specification on output pins c io ? ? 50 pf electrical character istics (continued) electrical characteristics: unless otherwise noted, v dd = 5v for l/m versions, v dd = 3.3v for t/s versions, v dd = 3v for r version, t a = -40c to +125c. typical values are at t a = +25c. parameter sym min typ (1) max units test conditions note 1: data in the typical (?typ?) column is at 5v, +25 c, unless otherwise stated. 2: r st output for tc1270a, and tc127 0an, rst output for tc1271a. 3: tc127xa refers to either the tc1270a, tc1270an or tc1271a device. 4: hysteresis is within the v trip(min) to v trip(max) window. 5: custom ordered voltage trip point. minimum order volume requirement. 6: this specification allows this device to be used in pic? microcontroller applications that require the in-circuit serial programming? (icsp?) feature (s ee device-specific programming specifications for voltage requirements). the total time that the rst pin can be above the maximum device operational voltage (5.5v) is 100s. current into the rst pin sh ould be limited to 2 ma. it is recommended that the device operational temperature be maintained between 0c to +70c (+25c preferred). for additional information, refer to figure 2-41 .
tc1270a/70an/71a ds22035b-page 4 ? 2007 microchip technology inc. 1.1 ac characteristics 1.1.1 timing parameter symbology the timing parameter sy mbols have been created following one of the following formats: figure 1-1: test load conditions 1. tpps2pps 2. tpps t f frequency t time e error lowercase letters (pp) and their meanings: pp io input or output pin osc oscillator rx receive tx transmit bitclk rx/tx bitclk rst reset drt device reset timer uppercase letters and their meanings: s f fall p period h high r rise i invalid (high-impedance) v valid l low z high-impedance pin v ss c l = 50 pf
? 2007 microchip technology inc. ds22035b-page 5 tc1270a/70an/71a 1.1.2 timing diagrams and specifications figure 1-2: mr pin and reset pin waveform figure 1-3: device voltage and reset pin (active low) waveform table 1-1: reset and device reset timer requirements electrical characteristics: unless otherwise noted, v dd = 5v for l/m versions, v dd = 3.3v for t/s versions, v dd = 3v for r version, t a = -40c to +125c. typical values are at t a = +25c. parameter sym min typ (1) max units test conditions v dd to reset delay t rd ?50?sv dd = v trip(max) to v trip(min) ?125 mv reset active timeout period tc127xax b vyy (3) t rst 1.09 2.19 4.38 ms v dd = v trip(max) tc127xax c vyy (3) 17.5 35 70 ms v dd = v trip(max) tc127xaxvyy (3) 140 280 560 ms v dd = v trip(max) mr minimum pulse width t mr 10 ? ? s mr noise immunity t mrni ?0.1? s mr to reset propagation delay t md ?0.2? s note 1: unless otherwise stated, data in the typical (?typ?) column is at 5v, +25 c. 2: rst output for tc1270a, rst output for tc1271a. 3: tc127xa refers to either the tc1270a, tc1270an or tc1271a device. ?x? indicated the selected voltage trip point, while ?yy? indicates the package code. mr rst t rst t mr rst t md t mrni v trip(max) v trip(min) 1v v dd v trip t rst rst (1) rst t rst t rd v dd < 1v is outside the device operating specification. the rst (or rst ) output state is unknown while v dd < 1v. note 1: the tc1270an requires an external pull-up resistor.
tc1270a/70an/71a ds22035b-page 6 ? 2007 microchip technology inc. temperature characteristics electrical specifications: unless otherwise indicated, v dd = +1.0v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ja ?256?c/w thermal resistance, 4l-sot-143 ja ?426?c/w
? 2007 microchip technology inc. ds22035b-page 7 tc1270a/70an/71a 2.0 typical performance curves note: unless otherwise indicated, all limits are specified for v dd = 1v to 5.5v, t a = ?40c to +125c. figure 2-1: i dd vs. temperature (reset power-up timer inactive) (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-2: i dd vs. temperature (reset power-up timer inactive) (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-3: i dd vs. temperature (reset power-up timer inactive) (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). figure 2-4: i dd vs. temperature (reset power-up timer active) (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-5: i dd vs. temperature (reset power-up timer active) (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-6: i dd vs. temperature (reset power-up timer active) (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). note: the graphs and tables provided following this note ar e a statistical summary based on a limited number of samples and are provided for informational purposes on ly. the performance characteristics listed herein are not tested or guaranteed. in some graphs or t ables, the data presented ma y be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0 0.5 1 1.5 2 2.5 -40 -20 0 20 40 60 80 100 120 temperature (c) i dd (a) 1.0v 2.0v 3.0v 4.0v 5.0v 0 0.5 1 1.5 2 2.5 3 -40 -20 0 20 40 60 80 100 120 temperature (c) i dd (a) 1.0v 2.0v 3.0v 4.0v 5.0v 0 0.5 1 1.5 2 2.5 3 -40 -20 0 20 40 60 80 100 120 temperature (c) i dd (a) 1.0v 2.0v 3.0v 4.0v 5.0v 4.5 5 5.5 6 6.5 7 -40 -20 0 20 40 60 80 100 120 temperature (c) i dd (a) 4.8v 5.5v 3 3.5 4 4.5 5 5.5 6 6.5 7 -40 -20 0 20 40 60 80 100 120 temperature (c) i dd (a) 4.5v 5.5v 3.5v 2.5 3 3.5 4 4.5 5 5.5 6 6.5 -40 -20 0 20 40 60 80 100 120 temperature (c) i dd (a) 4.0v 5.0v 3.0v
tc1270a/70an/71a ds22035b-page 8 ? 2007 microchip technology inc. note: unless otherwise indicated, all limits are specified for v dd = 1v to 5.5v, t a = ?40c to +125c. figure 2-7: i dd vs. v dd (reset power-up timer inactive) (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-8: i dd vs. v dd (reset power-up timer inactive) (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-9: i dd vs. v dd (reset power-up timer inactive) (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). figure 2-10: i dd vs. v dd (reset power-up timer active) (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-11: i dd vs. v dd (reset power-up timer active) (tc1270at, tc1270an t, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-12: i dd vs. v dd (reset power-up timer active) (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). 0 0.5 1 1.5 2 2.5 3 12345 v dd (v) i dd (a) -40c +125c +25c 0 0.5 1 1.5 2 2.5 3 12345 v dd (v) i dd (a) -40c +125c +25c 0 0.5 1 1.5 2 2.5 3 3.5 12345 v dd (v) i dd (a) -40c +125c +25c 4.5 5 5.5 6 6.5 7 4.5 4.7 4.9 5.1 5.3 5.5 v dd (v) i dd (a) -40c +125c +25c 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 33.544.555.5 v dd (v) i dd (a) -40c +125c +25c 2 3 4 5 6 7 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i dd (a) -40c +125c +25c
? 2007 microchip technology inc. ds22035b-page 9 tc1270a/70an/71a note: unless otherwise indicated, all limits are specified for v dd = 1v to 5.5v, t a = ?40c to +125c. figure 2-13: v trip and v hys vs. temperature (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-14: v trip and v hys vs. temperature (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-15: v trip and v hyst vs. temperature (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). figure 2-16: v ol vs. i ol (tc1270al, tc1270an l, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-17: v ol vs. i ol (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-18: v ol vs. i ol (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). 4.605 4.61 4.615 4.62 4.625 4.63 4.635 4.64 4.645 4.65 -40 25 125 temperature (c) v trip (v) 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0.4 v hys (%) v trip (with v dd falling) v hys v trip (with v dd rising) 3.066 3.068 3.07 3.072 3.074 3.076 3.078 3.08 3.082 3.084 3.086 -40 25 125 temperature (c) v trip (v) 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0.4 v hys (%) v hys v trip (with v dd falling) v trip (with v dd rising) 2.61 2.615 2.62 2.625 2.63 2.635 2.64 -40 25 125 temperature (c) v trip (v) 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0.4 v hys (%) v hys v trip (with v dd falling) v trip (with v dd rising) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.00 1.00 2.00 3.00 4.00 i ol (ma) v ol (v) 2.0v 3.0v 4.3v 4.4v 4.5v 0 0.05 0.1 0.15 0.2 0.25 02468 i ol (ma) v ol (v) 3.2v 4.0v 4.5v 5.0v 5.5v 3.15 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 01234 i ol (ma) v ol (v) 2.0v 2.45v 2.5v
tc1270a/70an/71a ds22035b-page 10 ? 2007 microchip technology inc. note: unless otherwise indicated, all limits are specified for v dd = 1v to 5.5v, t a = ?40c to +125c. figure 2-19: v ol vs. temperature (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). @ v dd = 4.5v). figure 2-20: v ol vs. temperature (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). @ v dd = 2.7v). figure 2-21: v ol vs. temperature (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). @ v dd = 1.8v). figure 2-22: v oh vs. i ol (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.) @ +25c). figure 2-23: v oh vs. i oh (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.) @ +25c). figure 2-24: v oh vs. i oh (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.) @ +25c). 0 0.02 0.04 0.06 0.08 0.1 0.12 -40 10 60 110 temperature (c) v ol (v) 4 ma 2 ma 1 ma 0.5 0.35 ma 0.2 a 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 -40 10 60 110 temperature (c) v ol (v) 8 ma 6 ma 4 ma 2 ma 1 ma 0.5 a 0 0.05 0.1 0.15 0.2 -40 10 60 110 temperature (c) v ol (v) 4 ma 2 ma 1 ma 0.5 0.35 ma 0.2 a 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 0.00 1.00 2.00 3.00 4.00 5.00 i oh (ma) v oh (v) 5.5v 5.0v 4.8v 4.75v 1.7 1.9 2.1 2.3 2.5 2.7 2.9 012345 i oh (ma) v oh (v) 2.9v 2.7v 2.5v 2 2.5 3 3.5 4 4.5 5 5.5 6 012345 i oh (ma) v oh (v) 5.5v 5.0v 4.5v 4.0v 3.0v 2.8v
? 2007 microchip technology inc. ds22035b-page 11 tc1270a/70an/71a note: unless otherwise indicated, all limits are specified for v dd = 1v to 5.5v, t a = ?40c to +125c. figure 2-25: v dd falling to reset propagation delay (t rpd ) vs. temperature (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-26: v dd falling to reset propagation delay (t rpd ) vs. temperature (tc1270at, tc1270an t, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-27: v dd falling to reset propagation delay (t rpd ) vs. temperature (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). figure 2-28: reset timeout period (t rst ) vs. temperature (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-29: reset timeout period (t rst ) vs. temperature (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-30: reset timeout period (t rst ) vs. temperature (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). 48 49 50 51 52 53 54 55 -40 10 60 110 temperature (c) t rpd (s) 48 49 50 51 52 53 54 55 -40 10 60 110 temperature (c) t rpd (s) 48 49 50 51 52 53 54 55 -40 10 60 110 temperature (c) t rpd (s) 275 280 285 290 295 300 305 310 315 320 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.75v 275 280 285 290 295 300 305 310 315 320 325 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.5v 4.0v 3.2v 3.15 275 280 285 290 295 300 305 310 315 320 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.5v 4.0v 3.0v 2.8v
tc1270a/70an/71a ds22035b-page 12 ? 2007 microchip technology inc. note: unless otherwise indicated, all limits are specified for v dd = 1v to 5.5v, t a = ?40c to +125c. figure 2-31: reset timeout period (t rst ) (c timeout option) vs. temperature (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-32: reset timeout period (t rst ) (c timeout option) vs. temperature (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-33: reset timeout period (t rst ) (c timeout option) vs. temperature (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). figure 2-34: reset timeout period (t rst ) (b timeout option) vs. temperature (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-35: reset timeout period (t rst ) (b timeout option) vs. temperature (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-36: reset timeout period (t rst ) (b timeout option) vs. temperature (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). 34 35 36 37 38 39 40 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.75v 34 35 36 37 38 39 40 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.5v 4.0v 3.2v 3.15v 34 35 36 37 38 39 40 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.5v 4.0v 3.0v 2.8v 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.75v 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.5v 4.0v 3.2v 3.15v 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 -40 10 60 110 temperature (c) t rst (ms) 5.5v 5.0v 4.5v 4.0v 3.0v 2.8v
? 2007 microchip technology inc. ds22035b-page 13 tc1270a/70an/71a note: unless otherwise indicated, all limits are specified for v dd = 1v to 5.5v, t a = ?40c to +125c. figure 2-37: mr low to reset propagation delay (t md ) vs. temperature (tc1270al, tc1270anl, tc1271al - 4.50v min. / 4.63v typ. / 4.75v max.). figure 2-38: mr low to reset propagation delay (t md ) vs. temperature (tc1270at, tc1270ant, tc1271at - 3.00v min. / 3.08v typ. / 3.15v max.). figure 2-39: mr low to reset propagation delay (t md ) vs. temperature (tc1270ar, tc1270anr, tc1271ar - 2.55v min. / 2.63v typ. / 2.70v max.). figure 2-40: v dd transient duration vs. reset threshold overdrive (v trip (minimum) - v dd ). figure 2-41: open-drain leakage current vs. voltage applied to rst pin (tc1270ar, tc1270anr, tc1271ar - 2.55v minimum). 0.17 0.18 0.19 0.2 0.21 0.22 -40 10 60 110 temperature (c) t md (s) 5.5v 5.0v 4.8v 4.75v 0.17 0.18 0.19 0.2 0.21 0.22 -40 10 60 110 temperature (c) t md (s) 5.5v 5.0v 4.5v 4.0v 0.17 0.18 0.19 0.2 0.21 0.22 -40 10 60 110 temperature (c) t md (s) 5.5v 5.0v 4.5v 4.0v 0 10 20 30 40 50 60 0.001 0.01 0.1 1 10 v tripmin - v dd (v) transient duration (s) 4.63v 3.08v 2.63v above line, reset occurs below line, no reset occurs 1.e-14 1.e-12 1.e-10 1.e-08 1.e-06 1.e-04 1.e-02 01234567891011121314 output voltage (v) leakage current (a) -40c +25c +125c 13.5v
tc1270a/70an/71a ds22035b-page 14 ? 2007 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: pinout description pin number sym pin standard function tc1270a (push-pull, active low) tc1270an (open-drain, active low) tc1271a (push-pull, active high) sot-23-5 sot-143-4 sot-23-5 sot-23-5 sot-143-4 type buffer / driver 51 51 v ss ? power ground 42 ? ? ?rst opush- pull reset output (push pull), active low h = v dd > v trip , reset pin is inactive (after reset timer delay completes) l = v dd < v trip , reset pin is active goes active (low) if one of these conditions occurs: 1. if v dd falls below the selected reset voltage threshold. 2. if the mr pin is forced low. 3. during power-up. ? ?4 ? ?rst o open- drain reset output (open-drain), active low float = v dd > v trip , reset pin is inactive (after reset timer delay completes) l = v dd < v trip , reset pin is active goes active (low) if one of these conditions occurs: 1. if v dd falls below the selected reset voltage threshold. 2. if the mr pin is forced low. 3. during power-up. ? ? ?42rstopush- pull reset output (push pull), active high h = v dd < v trip , reset pin is active l = v dd > v trip , reset pin is inactive (after reset timer delay completes) goes active (high) if one of these conditions occurs: 1. if v dd falls below the selected reset voltage threshold. 2. if the mr pin is forced low. 3. during power-up. note 1: the mr pin has an internal weak pull-up (18.5 k typical).
? 2007 microchip technology inc. ds22035b-page 15 tc1270a/70an/71a 33 ? 33mr ist (1) manual reset input pin this input allows a push button switch to be directly connected to the tc1270a/70an/71a?s mr pin, which can then be used to force a system reset. the input fil- ter (ignores) noise pulses that occur on the mr pin. h = switch is open (internal pull-up resistor pulls signal high). state of the rst/rst pin determined by other system condi- tions. l = switch is depressed (shorted to ground). this forces the rst/rst pin active. 24 ? 24v dd ? power supply voltage 1 ?? 1 ? nc ? ? no connection table 3-1: pinout description (continued) pin number sym pin standard function tc1270a (push-pull, active low) tc1270an (open-drain, active low) tc1271a (push-pull, active high) sot-23-5 sot-143-4 sot-23-5 sot-23-5 sot-143-4 type buffer / driver note 1: the mr pin has an internal weak pull-up (18.5 k typical).
tc1270a/70an/71a ds22035b-page 16 ? 2007 microchip technology inc. 3.1 ground terminal (v ss ) v ss provides the negative reference for the analog input voltage. typically, the circuit ground is used. 3.2 supply voltage (v dd ) v dd can be used for power supply monitoring or a voltage level that requires monitoring. 3.3 reset output (rst and rst ) there are three types of re set output pins. these are: 1. push-pull active-low reset 2. push-pull active-high reset 3. open-drain active-low reset, external pull-up resistor required. 3.3.1 active-low (rst ) - push-pull the rst push-pull output remains low while v dd is below the reset voltage threshold (v trip ). the time that the rst pin is held low after the device voltage (v dd ) returns to a high level (> v trip ) is typically 280 ms. after the reset delay ti mer expires, the rst pin will be driven to the high state. 3.3.2 active-high (rst) - push-pull the rst push-pull output remains high while v dd is below the reset voltage threshold (v trip ). the time that the rst pin is held high after the device voltage (v dd ) returns to a high level (> v trip ) is typically 280 ms. after the reset delay timer expires, the rst pin will be driven to the low state. 3.3.3 active-low (rst ) - open-drain the rst open-drain output remains low while v dd is below the reset voltage threshold (v trip ). the time that the rst pin is held low after the device voltage (v dd ) returns to a high level (> v trip ) depends on the reset timeout selected. after the reset delay timer expires, the rst pin will float. 3.4 manual reset input (mr ) the manual reset (mr ) input pin allows a push button switch to easily be connected to t he system. when the push button is depressed, it forces a system reset. this pin has circuitry that filters noise that may be present on the mr signal. the mr pin is active-low and has an internal pull-up resistor.
? 2007 microchip technology inc. ds22035b-page 17 tc1270a/70an/71a 4.0 device operation 4.1 general description for many of today?s microc ontroller applications, care must be taken to prevent low-power conditions that can cause many different system problems. the most common causes are brown-out conditions, where the system supply drops below the operating level momentarily. the second most common cause is when a slowly decaying power supply causes the microcon- troller to begin executing in structions without sufficient voltage to sustain volati le memory (ram), thus producing indeterminate results. the tc127xa family (tc1270a, tc1270an, and tc1271a) are cost-effective voltage supervisor devices designed to keep a microcontroller in reset until the system voltage ha s reached and stabilized at the proper level for reliable system operation. these devices also operate as protection from brown-out conditions when the system supply voltage drops below a safe operating level. a manual reset input (mr pin) is provided. this allows a push button switch to be directly connected to the tc127xa device, and is suitable for use as a push button reset. this allows t he system to easily be reset from the external control of the push button switch. no external components are required. the reset pin (rst or rst ) will be forced active, if any of the following occur: ? during device power up ?v dd goes below the device threshold voltage ? the manual reset input (mr ) goes low figure 4-1 shows a high level block diagram of the devices. the device can be described with three functional blocks. these are: ? voltage detect circuit ? manual reset with glitch filter circuit ? reset generator circuit the reset generator circuit controls the reset delay time of the reset output signal. there are three reset delay time options. depending on the option, the reset signal (rst /rst pin) will be held active for a minimum of 1.09 ms, 17.5 ms, or 140 ms. the tc1271a has an active-high rst output while the tc1270a and tc1270an have an active-low r st output. the tc1270a and tc1271a have a push-pull output driver, while the tc1270a n has an open-drain output. figure 4-2 shows a typical circuit for a push-pull device and figure 4-3 shows a typical circuit for an open-drain device. figure 4-1: tc127xa high level block diagram. figure 4-2: typical push-pull application circuit. figure 4-3: typical open-drain application circuit. the tc1270a and tc1271a devices are available in a 4-pin sot-143 package to maintain footprint compati- bility with the tc1270, tc1271, tcm811, and tcm812 devices, and the sot-23-5 package. the tc1270an is only available in the sot-23-5 package. low supply current makes these devices suitable for battery powered applications. device specific block diagrams are shown in figure 4-4 through figure 4-6 . v dd mr rst rst voltage detector reset circuit manual reset with glitch filter circuit generator circuit or vrst mrrst push button mr v ss v ss v dd v dd reset input tc1270a/1a v dd 0.1 f rst or rst push button mr v ss v ss v dd v dd rst reset input tc1270an v dd 0.1 f
tc1270a/70an/71a ds22035b-page 18 ? 2007 microchip technology inc. figure 4-4: tc1270a block diagram. figure 4-5: tc1270an block diagram. figure 4-6: tc1271a block diagram. 4.2 voltage detect circuit the voltage detect circuit monitors v dd . the device?s reset voltage trip point (v trip ) is selected when the device is ordered. the voltage on the device?s v dd pin determines the output state of the rst /rst pin. v dd voltages above the v trip(max) force the rst /rst pin inactive. v dd voltages below the v trip(min) force the rst /rst pin active. the state of the rst /rst pin is unknown for v dd voltages between v trip(max) and v trip(min) . this is shown in ta b l e 4 - 1 table 4-1: v dd levels to rst /rst output states the term v trip will be used as the general term for the trip point voltage where the device actually trips. in the case where v dd is falling (for voltages starting above v trip(max) ): ? voltages above v trip(max) will never cause the rst /rst output pin to be driven active. ? voltages below v trip(min) will always cause the rst /rst output pin to be driven active. now in the case where v dd is rising (for voltages starting below v trip(min) ): ? voltages above v trip(max) will always cause the rst /rst output pin to be driven inactive, (or floated - tc1270an) after the reset delay timer (t rst ), times out. v dd comparator + ? output driver rst reference noise filter mr voltage delay (push- pull) v dd comparator + ? rst reference v ss noise filter mr voltage delay output driver (open- drain) v dd comparator + ? rst reference noise filter mr voltage delay output driver (push- pull) v dd voltage level output state rst rst v dd v trip(max) h (1, 2) l (1) v trip(min) < v dd < v trip(max) uu v dd v trip(min) lh legend: h = driven high l = driven low u = unknown, driven either high or low note 1: the rst /rst pin will be driven inactive after the reset delay timer (t rst ) times out. 2: the tc1270an rst pin will be floated after the reset delay timer (t rst ) times out.
? 2007 microchip technology inc. ds22035b-page 19 tc1270a/70an/71a table 4-2 shows the various device trip point options and their v trip(max) and v trip(min) voltages. also the negative percentage change from common regulated voltages is shown. in the case where v dd is falling from the regulated volt- age, as the v dd crosses the v trip voltage the rst /rst pin is driven active. now the desired circuitry is in reset, or the circuitry has the indication that the v dd is below the selected v trip . in the case where v dd is rising. as the v dd crosses the v trip voltage, the rst /rst pin is driven inactive after the reset delay timer elapses. now the desired cir- cuitry is released from reset and will start to operate in its normal mode, or the circuitry has the indication that the v dd is above the selected v trip . table 4-2: selecting the trip point the tc1270a/tc1270an/tc1271a devices are optimized to reject fast tr ansient glitches on the v dd line. if the low input signal (which is below v trip ) is not rejected, the reset output is driven active within 50 s of v dd falling through the reset voltage threshold. after the device exits the reset condition, the delay circuitry will hold the rst /rst pin active until the appropriate reset delay time (t rst ) has elapsed. during device power up, the input voltage is below the trip point voltage. the device must enter the valid operating range for the device to start operation. 4.2.1 hysteresis there is also a minimal hysteresis (v hys ) on the trip point. this is so that small noise signals on the device voltage (v dd ) do not cause the reset pin (rst /rst) to ?jitter? (change between driving an active and inactive). the characterization graphs shown in figures 2-13 through 2-15 shows the device hysteresis as a percent- age of the voltage trip point (v trip ). the reset delay timer (t rst ) gives a time based hys- teresis for the system. 4.2.2 power-up/rising v dd as the device v dd rises, the device?s reset circuit will remain active until the voltage rises above the ?actual? trip point (v trip ). figure 4-7 shows a power-up sequence and the wave- form of the rst and rst pins. as the device powers up, the voltage will start below the valid operating volt- age of the device. at this voltage, the rst /rst output is not valid. once the voltage is above the minimum operating voltage (1v) and below the selected v trip , the reset output will be active. once the device voltage rises above the v trip voltage, the reset delay timer (t rst ) starts. when the reset delay timer times out, the reset output (rst /rst) is driven inactive. figure 4-7: rst /rst pin operation power-up. trip voltage selection v trip(max) (1) / v trip(min) (2) - % from regulated voltage 5.0v 3.3v 3.0v l 4.75v 5.0% ? ? 4.50v 10.0% ? ? m 4.50v 10.0% ? ? 4.25v 15.0% ? ? t3.15v?4.5%? 3.00v ? 9.2% ? s3.00v?9.2%? 2.85v ? 13.7% ? r 2.70v ? ? 10.0% 2.55v ? ? 15.0% note 1: voltage regulator circuit must have tighter tolerance (%) than v trip(max) % from regulated voltage. 2: circuitry being reset must have a wider tolerance (%) than v trip(min) % from regulated voltage. v trip 1v v dd t rst (1) rst (2) rst note 1: additional system current is consumed during the t rst time. 2: the tc1270an requires an external pull-up resistor.
tc1270a/70an/71a ds22035b-page 20 ? 2007 microchip technology inc. 4.2.3 power-down/brown-outs as the device powers-down/brown-outs, the v dd falls from a voltage above the devices trip point (v trip ). the device will trip at a voltage between the maximum trip point (v trip(max) ) and the minimum trip point (v trip(min) ). once the device voltage (v dd ) goes below this voltage, the rst /rst pin will be forced to the active state. figure 4-8 shows the waveform of the rst pin as determined by the v dd voltage. as the v dd voltage falls from the normal operating point, the device ?enters? reset by crossing the v trip voltage (between v trip(max) and v trip(min) ). then when v dd voltage rises, the device ?exits? reset by crossing the v trip volt- age (below or at v trip(max) ). after the ?exit? state has been detected, the reset delay timer (t rst ) starts. once the t rst time completes, the reset pin is driven inactive. table 4-3 shows the state of the rst or rst pins. table 4-3: reset pin states figure 4-8: rst operation as determined by the v trip . device state of rst pin when: state of rst pin when: output driver v dd < v trip v dd > v trip (1) v dd < v trip v dd > v trip (1) tc1270a l h ? ? push-pull tc1271a ? ? h l push-pull note 1: the rst /rst pin will be driven inactive after the reset delay timer (t rst ) times out. v dd v trip rst (1) 1v < 1v is outside the device specifications t rd t rst t rd t rst v trip (with v dd falling) (with v dd rising) note 1: the tc1270an requires an external pull-up resistor.
? 2007 microchip technology inc. ds22035b-page 21 tc1270a/70an/71a 4.3 negative going v dd transients the minimum pulse width (time) required to cause a reset may be an important criteria in the implementa- tion of a power-on reset (por) circuit. this time is referred to as transient duration. the tc127xa devices are designed to reject a level of negative-going transients (glitches) on the power supply line. transient duration is the amount of time needed for these supervisory devices to respond to a drop in v dd . the transient duration time (t tran ) is dependent on the magnitude of v trip ? v dd (overdrive). any combination of duration and overdrive that lies under the duration/overdrive curve will not generate a reset signal. generally speaking, the transient duration time decreases with an increase in the v trip ? v dd voltage. figure 4-9 shows an example transient duration vs. reset comparator overdrive. it shows that the farther below the trip point the transient pulse goes, the duration of the pulse required to cause a reset gets shorter. so any combination of duration and overdrive that lays under the curve will not generate a reset signal. combinations above the curve are detected as a brown-out or power-down. transient immunity can be improved by adding a bypass capacitor (typically 0. 1 f) as close as possible to the v dd pin of the tc127xa device. figure 4-9: example of typical transient duration waveform. 4.4 manual reset with glitch filter circuit the manual reset input pin (mr ) allows the reset pins (rst/rst ) to be manually forced to their active states. the mr pin has circuitry to filter noise pulses that may be present on the pin. figure 4-10 shows a block diagram for using the tc127xa with a push button switch. to minimize the required external components, the mr input has an internal pull-up resistor. a mechanical push button or active logic signal can drive the mr input. once mr has been low for a time, t md (the manual reset delay time), the reset output pins are forced active. the reset output pins will remain in their active states for the reset delay timer time out period (t rst ). figure 4-11 shows a waveform for the manual reset switch input and the reset pins output. figure 4-10: push button reset. figure 4-11: mr input ? push button. 4.4.1 noise filter the noise filter filters out noi se spikes (glitches) on the manual reset pin (mr ). noise spikes less than 100 ns (typical) are filtered. time (s) 0v supply voltage 5v v trip(min) - v dd t tran (duration) v trip(max) v trip(min) (overdrive) transient overdrive voltage (mv) transient duration (ms) area below curve will not generate a reset signal area above curve will generate a reset signal v dd mr v ss rst mclr +5v tc127xa pic ? mcu rst v il t mr rst t md v ih t rst mr the mr input typically ignores input pulses of 100 ns.
tc1270a/70an/71a ds22035b-page 22 ? 2007 microchip technology inc. 4.5 reset generator circuit the output signals from the voltage detect circuit and the manual reset with glitch filter circuit are or?d together and is used to activate the reset generator module. after the reset conditions have been removed (the mr pin is no longer forced low and the input voltage is greater than the trip point voltage), the reset genera- tor circuit determines the reset delay timeout required. there are three options for the delay circuit. these are: ? 2.19 ms (typical) delay ? 35 ms (typical) delay ? 280 ms (typical) delay 4.5.1 reset delay timer the reset delay timer ensures that the tc127xa device will ?hold? the embedded system in reset until the system voltage has st abilized. the reset delay timer time out is shown in ta b l e 4 - 4 . the reset delay timer starts once the voltage detector circuit output and the manual reset with glitch filter circuit output become inactive. while the reset delay timer is active, the rst or rst pin is driven to the active state. once the reset delay timer times-out, the rst or rst pin is driven inactive. the reset delay timer (t rst ) starts after the device voltage rises above the ?actual? trip point (v trip ). when the reset delay timer times out, the reset output pin (rst/rst ) is driven inactive. the reset delay timer is clear ed, if either (or both) the voltage detector circuit output or the manual reset with glitch filter circuit output become active. the rst or rst pin continues to be driven to the active state. figure 4-12 illustrates when the reset delay timer (t rst ) is active or inactive. 4.5.2 effect of temperature on reset power-up timer (t rpu ) the reset delay timer time out period (t rst ) determines how long the device remains in the reset condition. this time out is affected by both the device v dd and temperature. typical responses for different v dd values and temperatures are shown in figures 2-28 , 2-29 and 2-30 . table 4-4: reset delay timer time outs figure 4-12: reset power-up timer waveform. t rst units min typ max 1.09 2.19 4.38 ms 17.5 35 70 ms 140 280 560 ms this is the minimum time that the reset delay timer will ?hold? the reset pin active after v dd rises above v trip this is the maximum time that the reset delay timer will ?hold? the reset pin active after v dd rises above v trip note 1: shaded rows are custom ordered time outs. v trip v dd rst t rst reset delay timer inactive reset delay timer inactive reset delay timer active see figures 2-9 , 2-7 and 2-8 see figures 2-12 , 2-11 and 2-10 see figures 2-9 , 2-7 and 2-8
? 2007 microchip technology inc. ds22035b-page 23 tc1270a/70an/71a 5.0 application information this section shows application related information that may be useful for your particular design requirements. 5.1 supply monitor noise sensitivity the tc127xa devices are optimized for fast response to negative-going changes in v dd . systems with an inordinate amount of electrical noise on v dd (such as systems using relays) may require a 0.01 f or 0.1 f bypass capacitor to reduce detection sensitivity. this capacitor should be installed as close to the tc127xa as possible to keep the capacitor lead length short. figure 5-1: typical application circuit with bypass capacitor. 5.2 conventional voltage monitoring figure 5-2 and figure 5-3 show the tc127xa in conventional voltage monitoring applications. figure 5-2: battery voltage monitor. figure 5-3: power good monitor. 5.3 using in pic ? microcontroller, icsp? applications figure 5-4 shows the typical application circuit for using the tc1270an for voltage supervisory function when the pic microcontroller will be programmed via the in-circuit serial progra mming? (icsp?) feature. additional information is available in tb087, ?using voltage supervisors with picmicro ? microcontroller systems which implement in-circuit serial program- ming?? , ds91087. figure 5-4: typical application circuit for pic ? microcontroller with the icsp? feature. tc127xa v dd rst v ss 0.1 f rst mr v dd rst v ss batlow tc127xa + ? ? v dd rst v ss power good tc127xa + ? pwr sply note: this operation can only be done using the device with the open-drain rst pin (tc1270an). note: it is recommended that the current into the rst pin be current limited by a 1 k resistor. tc1270an v dd v dd /v pp v dd rst mclr reset input) (active-low) v ss v ss pic ? microcontroller r pu 0.1 f 1k
tc1270a/70an/71a ds22035b-page 24 ? 2007 microchip technology inc. 5.4 modifying the trip point, v trip although the tc127xa device has a fixed voltage trip point (v trip ), it is sometimes necessary to make custom adjustments. this can be accomplished by connecting an external resist or divider to the tc127xa v dd pin. this causes the v source voltage to be at a higher voltage than when the tc127xa input equals it?s v trip voltage ( figure 5-5 ). to maintain detector accuracy, the bleeder current through the divider should be significantly higher than the 15 a maximum operating current required by the tc127xa. a reasonable value for this bleeder current is 1 ma (67 times the 10 a required by the tc127xa). for example, if v trip = 2v and the desired trip point is 2.5v, the value of r 1 + r 2 is 2.5 k (2.5v/1 ma). the value of r 1 + r 2 can be rounded to the nearest stan- dard value and plugged into the equation of figure 5-5 to calculate values for r 1 and r 2 . 1% tolerance resis- tors are recommended. figure 5-5: modify trip-point using external resistor divider. 5.5 mosfet low-drive protection low operating power and small physical size make the tc1270an series ideal for many voltage detector applications. figure 5-6 shows a low-voltage gate drive protection circuit that pr events overheating of the logic-level mosfet due to insufficient gate voltage. when the input signal is below the threshold of the tc1270an, its output grounds the gate of the mosfet. figure 5-6: mosfet low-drive protection. tc127xa v dd rst v ss r 1 v source r 2 or rst v source r 1 r 1 r 2 + ------------------- - v trip = where: note: in this example, v source must be greater than (v trip ). v source = voltage to be monitored v trip = threshold voltage setting v dd rst v ss tc1270an 270 (1) mtp3055el v dd r l v trip note 1: this resistance needs to be properly sized for the selected trip point voltage related to the v ol operation.
? 2007 microchip technology inc. ds22035b-page 25 tc1270a/70an/71a 5.6 controllers and processors with bidirectional i/o pins some microcontrollers have bidirectional reset pins. depending on the current drive capability of the controller pin, an indeterminate logic level may result if there is a logic conflict. this can be avoided by adding a 4.7 k resistor in series with the output of the tc127xa ( figure 5-7 ). if there are other components in the system that require a reset signal, they should be buffered so as not to load the reset line. if the other components are required to follow the reset i/o of the microcontroller, the buffer should be connected as shown with the solid line. figure 5-7: interfacing the tc1270a or tc1271a push-pull output to a bidirectional reset i/o pin. 5.7 migration paths figure 5-8 shows the 5-pin sot-23 footprint of the tc1270a, tc1270an and tc1271a devices. devices that are in the 3-pin sot-23 package could be used in that circuit with the loss of the manual reset functionality. examples of co mpatible footprint devices in the sot-23-3 package are the mcp111, mcp112, tc54, and tc51 devices. this allows the system to be designed to offer a ?base? functionality and a higher end system with the ?enhanced? functi onality, which includes a manual reset. figure 5-8: sot-23 5-pin to 3-pin comparison. 5.8 reset signal integrity during power-down the tc1270a and tc1271a reset output is valid down to v dd = 1.0v. below this voltage the output becomes an ?open circuit? and does not sink current. this means cmos logic inputs to the microcontroller will be floating at an undetermined voltage. most digital systems are completely shut down well above this voltage. however, in situations where the reset signal must be maintained valid to v dd = 0v, external circuitry is required. for devices where the reset signal is active-low, a pull-down resistor must be connected from the tc1270a rst pin to ground to discharge stray capacitances and hold the output low ( figure 5-9 ). similarly for devices where the reset signal is active-high, a pull-up resistor to v dd is required to ensure a valid high rst signal for v dd below 1.0v ( figure 5-10 ). this resistor value, thoug h not critical, should be chosen such that it does not appreciably load the reset pin under normal operation (100 k will be suitable for most applications). figure 5-9: ensuring a valid active-low reset pin output state as v dd approaches 0v. figure 5-10: ensuring a valid active-high reset pin output state as v dd approaches 0v. mr v ss v ss v dd v dd rst reset i/o tc1270a/71a v dd or rst buffered reset to system 4.7 k 3 2 1 sot-23-3 1 2 3 5 4 sot-23-5 nc v dd mr rst v ss v ss v dd or rst rst or rst mr v ss v dd rst tc1270a v dd r 1 100 k mr v ss v dd rst tc1271a v dd r 1 100 k
tc1270a/70an/71a ds22035b-page 26 ? 2007 microchip technology inc. 6.0 standard devices table 6-1 shows the standard devices and their order number that are available and their respective configuration. the configuration includes the: ? voltage trip point (v trip ) ? reset time out (t rst ) table 6-1: standard versions device reset threshold (v) reset time out (ms) package order number replaces minimum typical maximum code minimum typical maximum code (1) tc1270a 4.50 4.63 4.75 l 140 280 560 ?blank? sot-23-5 tc1270alvcttr ? sot-143 tc1270alvrctr tc1270lerc / tcm811lerc tc1270a 4.25 4.38 4.50 m 140 280 560 ?blank? sot-23-5 tc1270amvcttr ? sot-143 tc1270amvrctr tc1270merc / tcm811merc tc1270a 3.00 3.08 3.15 t 140 280 560 ?blank? sot-23-5 tc1270atvcttr ? sot-143 tc1270atvrctr tc1270terc / tcm811terc tc1270a 2.85 2.93 3.00 s 140 280 560 ?blank? sot-23-5 tc1270asvcttr ? sot-143 tc1270asvrctr tc1270serc / tcm811serc tc1270a 2.55 2.63 2.70 r 140 280 560 ?blank? sot-23-5 tc1270arvcttr ? sot-143 tc1270arvrctr tc1270rerc / tcm811rerc tc1270an 4.50 4.63 4.75 l 140 280 560 ?blank? sot-23-5 tc1270anlvct ? tc1270an 4.25 4.38 4.50 m 140 280 560 ?blank? sot-23-5 tc1270anmvct ? tc1270an 3.00 3.08 3.15 t 140 280 560 ?blank? sot-23-5 tc1270antvct ? tc1270an 2.85 2.93 3.00 s 140 280 560 ?blank? sot-23-5 tc1270ansvct ? tc1270an 2.55 2.63 2.70 r 140 280 560 ?blank? sot-23-5 tc1270anrvct ? tc1271a 4.50 4.63 4.75 l 140 280 560 ?blank? sot-23-5 tc1271alvcttr ? sot-143 tc1271alvrctr tc1271lerc / tcm812lerc tc1271a 4.25 4.38 4.50 m 140 280 560 ?blank? sot-23-5 tc1271amvcttr ? sot-143 tc1271amvrctr tc1271merc / tcm812merc tc1271a 3.00 3.08 3.15 t 140 280 560 ?blank? sot-23-5 tc1271atvcttr ? sot-143 tc1271atvrctr tc1271terc / tcm812terc tc1271a 2.85 2.93 3.00 s 140 280 560 ?blank? sot-23-5 tc1271asvcttr ? sot-143 tc1271asvrctr tc1271serc / tcm812serc tc1271a 2.55 2.63 2.70 r 140 280 560 ?blank? sot-23-5 tc1271arvcttr ? sot-143 tc1271arvrctr tc1271rerc / tcm812rerc note 1: ?a? timeout delay options are only standard in t he sot-23-5 package. sot-143 package is a custom request.
? 2007 microchip technology inc. ds22035b-page 27 tc1270a/70an/71a 7.0 custom configurations the following custom reset trip point is available (see table 7-1 ). table 7-1: custom trip point table 7-2 shows the codes that specify the desired reset time out (t rst ) for custom devices table 7-2: delay time out ordering codes trip voltage selection v trip(max) / v trip(min) - % from regulated voltage 3.0v (1) 2.85v 5.0% 2.70v 10.0% note 1: contact factory for additional information. code reset delay time (typ) (ms) comment b 2.19 note 1 c 35 note 1 ?blank? 280 delay timings for standard device offerings note 1: this delay timing option is not the standard offering . for information on ordering devices with these delay times, contact your local microchip sales office. minimum purchase volumes are required.
tc1270a/70an/71a ds22035b-page 28 ? 2007 microchip technology inc. 8.0 development tools 8.1 evaluation/demonstration boards the sot-23-5/6 evaluation board (vsupev2) can be used to evaluate the charac teristics of the tc127xa devices. this blank pcb has footprints for: ? pull-up resistor ? pull-down resistor ? loading capacitor ? in-line resistor there is also a power supply filtering capacitor. for evaluating the tc127xa devices, the selected device should be installed into the option a footprint. figure 8-1: sot-23-5/6 voltage supervisor evaluati on board (vsupev2). the soic14-ev (102-00094) board has a sot-23-6 footprint, that can be jumper ed into any portion of the circuit. this will allow any footprint that the tc1270a requires in the sot-23-5 package. figure 8-2: soic-14 evaluation board (soic14ev). these boards may be purchased directly from the microchip web site at www.microchip.com.
? 2007 microchip technology inc. ds22035b-page 29 tc1270a/70an/71a 9.0 packaging information 9.1 package marking information 5-pin sot-23 part number code part number code tc1270alvcttr f1nn tc1271alvcttr j1nn tc1270amvcttr f2nn tc1271amvcttr j2nn tc1270atvcttr f3nn tc1271atvcttr j3nn tc1270asvcttr f4nn tc1271asvcttr j4nn tc1270arvcttr f5nn tc1271arvcttr j5nn tc1270anlvcttr fsnn tc1270anmvcttr ftnn tc1270antvcttr funn tc1270ansvcttr fvnn TC1270ANRVCTTR fwnn example: legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxnn f125 4-lead sot-143 xxnn example: c125 part number code part number code tc1270alvrctr d1nn tc1271alvrctr c1nn tc1270amvrctr d2nn tc1271amvrctr c2nn tc1270atvrctr d3nn tc1271atvrctr c3nn tc1270asvrctr d4nn tc1271asvrctr c4nn tc1270arvrctr d5nn tc1271arvrctr c5nn tc1270anlvrctr e1nn tc1270anmvrctr e2nn tc1270antvrctr e3nn tc1270ansvrctr e4nn tc1270anrvrctr e5nn
tc1270a/70an/71a ds22035b-page 30 ? 2007 microchip technology inc. 5-lead plastic small outline transistor (ct) [sot-23] notes: 1. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.127 mm per side. 2. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 5 lead pitch e 0.95 bsc outside lead pitch e1 1.90 bsc overall height a 0.90 ? 1.45 molded package thickness a2 0.89 ? 1.30 standoff a1 0.00 ? 0.15 overall width e 2.20 ? 3.20 molded package width e1 1.30 ? 1.80 overall length d 2.70 ? 3.10 foot length l 0.10 ? 0.60 footprint l1 0.35 ? 0.80 foot angle 0 ? 30 lead thickness c 0.08 ? 0.26 lead width b 0.20 ? 0.51 n b e e1 d 1 2 3 e e 1 a a1 a2 c l l1 microchip technology drawing c04-091b
? 2007 microchip technology inc. ds22035b-page 31 tc1270a/70an/71a 4-lead plastic small outline transistor (rc) [sot-143] notes: 1. significant characteristic. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 4 pitch e 1.92 bsc lead 1 offset e1 0.20 bsc overall height a 0.80 ? 1.22 molded package thickness a2 0.75 0.90 1.07 standoff a1 0.01 ? 0.15 overall width e 2.10 ? 2.64 molded package width e1 1.20 1.30 1.40 overall length d 2.67 2.90 3.05 foot length l 0.13 0.50 0.60 footprint l1 0.54 ref foot angle 0 ? 8 lead thickness c 0.08 ? 0.20 lead 1 width b1 0.76 ? 0.94 leads 2, 3 & 4 width b 0.30 ? 0.54 d e e /2 n e e1 2 1 e 1 a a1 b2 a2 3 x b c l l1 microchip technology drawing c04-031b
tc1270a/70an/71a ds22035b-page 32 ? 2007 microchip technology inc. 9.2 product tape and reel specifications figure 9-1: embossed carrier dimensions (8 mm tape only) figure 9-2: 5-lead sot-23 device tape and reel specifications to p cover tape k 0 p w b 0 a 0 table 1: carrier tape/cavity dimensions case outline package type carrier dimensions cavity dimensions output quantity units reel diameter in mm w mm p mm a0 mm b0 mm k0 mm ot sot-23 5l 8 4 3.2 3.2 1.4 3000 180 rc sot-143 4l 8 4 3.1 2.69 1.3 3000 180 us e r dir e ction of f ee d p, pitch standard r ee l compon e nt ori e ntation r e v e rs e r ee l compon e nt ori e ntation w, width of carri e r tap e pin 1 pin 1 d e vic e marking
? 2007 microchip technology inc. ds22035b-page 33 tc1270a/70an/71a figure 9-3: 4-lead sot-143 devi ce tape and reel specifications component taping orientation for 4-pin sot-143 devices pin 1 device marking user direction of feed standard reel component orientation for tr suffix device (mark right side up) w p carrier tape, number of components per reel and reel size: package carrier width (w) pitch (p) part per full reel reel size 4-pin sot-143 8 mm 4 mm 3000 7 in.
tc1270a/70an/71a ds22035b-page 34 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds22035b-page 35 tc1270a/70an/71a appendix a: revision history revision b (june 2007) ? added new options: - open-drain output - new reset delay timeouts. ? updated package outline drawings ? updated revision history ? added new options to product identification system revision a (march 2007) ? original release of this document.
tc1270a/70an/71a ds22035b-page 36 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds22035b-page 37 tc1270a//70an/71a product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: tc1270a: voltage supervisor with manual reset tc1270an: voltage supervisor with manual reset tc1271a: voltage supervisor with manual reset v trip options: r = 2.55v (min.) / 2.63v (typ.) / 2.70v (max.) s = 2.85v (min.) / 2.93v (typ.) / 3.00v (max.) t = 3.00v (min.) / 3.08v (typ.) / 3.15v (max.) m = 4.25v (min.) / 4.38v (typ.) / 4.50v (max.) l = 4.50v (min.) / 4.63v (typ.) / 4.75v (max.) time out options: b = t rst = 2.19 ms (typ) c=t rst = 35 ms (typ) ?blank? = t rst = 280 ms (typ) temperature range: v = -40c to +125c package: ct = plastic small outline transistor, sot-23, 5-lead rc = plastic small outline transistor, sot-143, 4-lead tape/reel option: tr = tape and reel examples: a) tc1270asvcttr: 2.85v min. / 2.93v typ. / 3.00v max. voltage trip point, push-pull active low reset, reset delay timer = 280 ms, 5-ld sot-23, tape and reel, -40c to +125c b) tc1270alvrctr: 4.50v min. / 4.63v typ. / 4.75v max. voltage trip point, push-pull active low reset, reset delay timer = 280 ms, 4-ld sot-143, tape and reel, -40c to +125c c) tc1270anmbvcttr: 4.25v min. / 4.38v typ. / 4.50v max. open-drain active low reset, reset delay timer = 2.19 ms, 5-lead sot-23, tape and reel, -40c to +125c d) tc1270anlcvct: 4.50v min. / 4.63v typ. / 4.75v max. open-drain active low reset, reset delay timer = 35 ms, 5-lead sot-23, -40c to +125c e) tc1271arvcttr: 2.55v min. / 2.63v typ. / 2.70v max. voltage trip point, push-pull active high reset, reset delay timer = 280 ms, 5-ld sot-23, tape and reel, -40c to +125c f) tc1271atvrctr: 3.00v min. / 3.08v typ. / 3.15v max. voltage trip point, push-pull active high reset, reset delay timer = 280 ms, 4-ld sot-143, tape and reel, -40c to +125c part no. x x x temperature v trip options device range x x package x tape/reel option x reset delay options
tc1270a//70an/71a ds22035b-page 38 ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. ds22035b-page 39 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip te chnology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwar e or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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